Non-commutative logical circuits



May 30, 1961 R. F. RUTZ 2,986,653

NON-COMMUTATIVE LOGICAL CIRCUITS Original Filed May 20, 1955 L16 9 5 2 ano 24 I 1 R2 d 40 I5 N 4| P "W-F T FIG.1 3

a b c d O 0 OFF OFF F| G 2 0 OFF ON 0 ON OFF I OFF OFF 19? g I02 |0| 915\ s -62 ,10 I05 I06 22 T24 l8 0 m4 N I08 b 23 d -1 P 20 |03 1 FIG. 3

FIG. 4 FIG. 5

a b c d o b c d O 0 ON OFF 0 '0 ON OFF l 0 OFF ON 0 OFF ON 0 l ON OFF 01 ON OFF 1 ON OFF I l OFF OFF INVENTOR RICHARD F. RUTZ ATTORNEY UnitedStates Patent F 2,986,653 I NON-COMMUTATIV E LOGICAL CIRCUITS Originalapplication May 20, 1955, Ser. No. 509,852. Divlded and this applicationJan. 31', 1958, Ser. No.

3 Claims. (Cl. 307-'88.5)

This is a division of my copending application Serial No. 509,852, filedMay 20, 195-5, entitled Multiple Col,- lector Transistors and CircuitsTherefor which is in turn a continuation in part of my application.Serial No. 35 8,- 619, filed September 27, 1954, now U.S. Patent No.2,889,499, entitled Transistor Circuit Element.

There are shown and described in said application Serial No. 458,619,transistors comprising a body of semi-con ductive material including twothin regions of substantially' equal area and of opposite conductivitytypes, the two regions being separated by a boundary junction. One ofthe two regions has a thickness substantially no greater than thediffusion length for the average lifetime of minority carriers in thematerial of that region. The second region has a resistivitysubstantially lower than (e.g approximately equal to one-tenth) that ofthe first region and'is sufficiently thin so that when provided with anohmic electrical connection over most of its area, there issubstantially no potential gradient throughout it. A high alphacollector is connected to the first-mentioned zone at the surfacethereof on the opposite side firom the junction. The junction, or partof it, serves as an emitter for minority carriers traveling toward thecollector. The flow of minority carriers from the junction is controlledby an electric field impressed across the higher resistivity region andeffective to produce a potential gradient therein which determines howgreat a proportion of the junction is forwardly biased so as to emitminority carriers.

In accordance with the invention claimed in my application Serial No.509,852, the transistors of my earlier application may be modified bythe addition of a second collector on the same side of the highresistivity region as the first collector. The distribution of currentflow between the two collectors is determined by an electric fieldimpressed across the region of higher resistivity.

The present invention concerns non-connnutative logical circuitsutilizing transistors ofthe type described.

An object of the present invention is to provide improvednon-commutative logical circuits employing transistors of the typedescribed.

The foregoing object is attained in the circuits described herein byproviding a transistor comprising a body of semi-conductive materialincluding two regions of substantially equal area and oppositeconductivity types sep arated by a boundary junction. A first one of theregions has "a resistivity substantially higher than the other and athickness substantially no greater than the difiiusion length for theaverage lifetime of minority carriers in the material of that region.Two collectors are in electrical contact with that first region on thesurface thereof opposite the junction, and are spaced apart by adistance substantially greater than the diffusion length. The boundaryjunction serves as an emitter for the two collectors. The

low resistivity region operates substantially 'at a fixed potentialthroughout its area. One of the two collectors is biased ON. Theemission of minority carriers firom the junction and hence the ON andOFF conditions of, the

two collectors is controlled by signal inputs connected to v theopposite ends of the high resistivity region and effective to controlthe potential gradient across that region, there by determining thepolarity and magnitude of the bias across the respective portions of thejunction opposite the respective collectors. Signal outputs areconnected to the. respective collectors.

Other objects and advantages of the invention will be come apparent froma consideration of the following specification and claims taken togetherwith the accom panying drawings.

In the drawings:

Fig. 1 is, an electrical wiring diagram of a non-commutative logicalcircuit embodying the invention;

Fig. 2 is a table illustrating the various logical signal inputandoutput conditions in the circuit of Fig; 1;

Fig. 3 is a wiring diagram of a modified non-commutative logical circuitembodying the invention; and

Figs. 4 and 5 are tables similar to Fig. 2, illustrating two difierentmodes of operation of the circuit of Fig. 3.

Figs. 1 and 2 There is shown in Fig. l a transistor generally indi;cated by the reference numeral 1 and including a semiconductive bodycomprising a region 2 of N type semiconductive. material and a region 3of P type semi-conductive material. These regionsare separated by abound.- ary junction 4. Two collectors 5 land 6 engage the surface ofthe N region 2 opposite the junction 4. The collectors 5 and 6 areseparated by a distance which is greater than the diffusion length forthe average lifetime of minority carriers in the N region 2, Thethickness of the N region 2 between the surface engaged by thecollectors 5 and 6 and the junction 4 must be substantially equal to orless than that diffusion length. v

The resistivity of N region 2 should be sufiiciently greater than thatof P region 3 to ensure eificient emission of minority carriers fromjunction 4. For example, a resistiv-ity of N region 2 equal to ten timesthe resistivity of P region? is considered suitable for the modificationdcscribed herein, unless otherwise specified. More specifically, aresistivity of 5 ohm-cm. may be used for region 2 and a resistivity of0.5 ohm-cm. for region 3. I

It will be readily understood that the order of the types of thesemi-conductive materials may be reversed, Le. region 2 may be made Ptype and region 3 N type. If so reversed, the same dimensional andresistivity limitations apply as described above. That is to say, thediffusion length of minority carriers in region 2 always deter.- minesthe dimensional limitations and region 2 always has a greaterresistivity than region 3.

The collectors. 5 and 6 may be electro-formed point contacts, or may beany other collector structure having an intrinsic current amplificationgreater than 1 and (for N type material) preferably greater than 1+b,where b=the mobility ratio of electrons and holes in the region 2. For Ptype material, the intrinsic current amplification is preferably greaterthan 1+1/b.

An ohmic electrical connection 8 is made to the upper surface of the Nregion 2 between the collectors 5 and 6 and additional ohmic connections9 and 10 are made to the. upper surface of N region 2 at its oppositeends. A broad ohmic electrical connection 11 extends over substantiallythe entire lower surface of the P region 3, The resistivity of region 3is low enough and that region is made thin enough so that, with the aidof the broad connection 11, the P region is operated as an equipotentialregion. Collector 5 is connected through av wire 16, a load resistor 40and a load supply battery 18 to ground. Output terminals 19 and 20 arerespectively connected to the collector 5 and to the negative terminalof battery Collector 6 is connected through a wire 21, a load rmistor 41and a load supply battery 23 to ground. Output terminals 24 and 25 arerespectively connected to the collector 6 and to the negative terminalof battery 23. The ohmic connection 9 is connected to ground through thesecondary winding 28 of an input transformer 29. The primary winding 30of input transformer 29 is connected to input terminals 3 1 and 32, oneof which is grounded.

Ohmic connection 10 is similally connected to the secondary winding 33of an input transformer 34 having a primary winding 35.. One terminal ofeach of the windings 32 and 35 is grounded. Primary winding 35 isconnected to input terminals 36 and 37.

, It will be recognized that in the construction of a transistor such astransistor 1, the collectors and 6 will not ave exactly equal impedanceand their locations will not be exactly equal with respect to theirspacing from the ohmic connection 8 and from the junction 4. Because ofsuch inequalities minority carries omitted from the junction 4 normallytend to ditfuse more readily to one of the collectors than to the other.Such an unbalance of the collectors may be readily introducedintentionally in the manufacture of the transistor, by a number ofdifferent expedients, such as positioning the ohmic connection 8 closerto one collector than to the other.

Operation of Fig. 1

Assume that the signals received at input terminals 30, 31 and 36, 37are of magnitudes and polarities such that an even potential gradient isthus established across the N region 2 with the right-hand end positive.The central portion of the N region which is at a median potential isconnected through a wire and a resistor 26 to the P region 3, so thatthe entire P region is substantially at that median potential. Theright-hand half of the junction 4 is then reversely biased, since the Pregion 3 is at a less positive potential than the potential above thejunction 4. On the other hand, the lefthand half of the junction 4 isforwardly biased, since the N region 2 above it is at a less positivepotential than the P region 3 below it. The left-hand half of thejunction may therefore serve as an emitter of holes into the N region 2.These holes are collected at the collector 5 and a large output currentpulse is produced, appearing as a signal at the output terminals 19 and20.

When current starts flowing through collector 5, the potential gradientproduced by the current in N region 2 may tend to increase the forwardpotential across the left-hand portion of junction 4, thereby increasingthe supply of holes. The resistor 26 elfectively limits the hole supply,preventing the action from being cumulative beyond a definite point, andimproving the switching speed.

If for any reason it is desired not to limit this cumula- 'tive actionin any particular instance, resistor 26 may be omitted.

After the positive input signal terminates, both terminals 9 and 10 areat ground potential, and the potential difference across the junction 4becomes very small. If the junction 4 continues to emit holes, thatemission is accompanied by a potential drop across resistor 26, so thatregion 3 becomes momentarily negative with respect to region 2, junction4 becomes reversely biased, and the emission stops, turning thetransistor OFF.

Now assume that the signals received at input terminals 30, 31 and 36,37 are of opposite polarities, such that a potential gradient isestablished across N region 2 with the left-hand end positive. Theoperation is analogous to that just described, except that the righthandhalf of the junction 4 is forwardly biased and the left-hand half isreversely biased so that a substantial output current flows throughcollector 6 and an output signal appears at terminals 24 and 25.

v The circuit illustrated in Fig. 1 is a non-commutative logicalcircuit. The relative values of the load resistors,

4 40 and 41 are selected so that collector 5 or 6, whichever has thegreater intrinsic current amplification, normally operates in thesaturation region. The normal condition of the output terminals 19 and20 is their OFF or non-signal producing condition.

The input signals at terminals 31 and 32 are indicated in the table ofFig. 2 in the column under the reference character a. The input signalsat terminals 36 and 37 are indicated in the column under the referencechar acter b. Output signals at terminals 19 and 20 are indicated in thecolumn under the reference character c, and output signals at theterminals 24 and are indicated in the column under the referencecharacter a.

The table of Fig. 2 shows the various combinations of input signals 'aand b and the resulting combinations of output signals c and d. It maybe seen that there are only two combinations of signals at inputterminals a and b which can shift the output signals from their normalcondition with the signal c off and the signal d off. These particularcombinations of input signals are with the signal a at its binary 1value (positive) and the signal b at its binary 0 value, and theconverse.

A binary 1 input signal may correspond, for example, to an inputpotential of +5 volts, while a binary 0 corre sponds to an inputpotential of 0 volts. When the input signals are in the conditionsillustrated in the second line of the table, the connection 9 issubstantially at +5 volts and the connection 10 is at ground potential.The left-hand half of the junction 4 is then reverse biased, andcollector 5 is OFF. If both of these two signal potentials shift fromthese values to the opposite values, as in line 3 of Fig. 6, then thecollector 5 is turned ON. As long as both input signals are the same atany value, then they counteract each other and do not disturb the normalcondition of the output signals.

It may therefore be seen that the circuit of Fig. l operates as anon-commutative logical circuit, in that only one of the possiblecombinations of input signals will operate to shift a given collectorfrom its normal output condition to a different output condition. Thecircuit therefore logically distinguishes that one particularcombination of input signals from all other possible combinations.

Figs. 3 to 5 Fig. 3 illustrates a non-commutative logical circuit usingthe same transistor 1 as the circuit of Fig. 1, but operating in asomewhat different manner. The input signals are resistively coupled tothe transistor in the circuit of Fig. 3 instead of being transformercoupled as in the circuit of Fig. 1. Furthermore, the junction 4 ispermanently biased forwardly. Those circuit elements of Fig. 3 which arethe same as those in Fig. l have been given the same reference numeralsand will not be further described. Load resistors 40 and 41 of Fig. 1,which may be unequal, are replaced by equal load resistors 17 and 22.

Ohmic connection 9 is connected through a resistor 101 to an inputterminal 102. Another input terminal 103 is grounded. Connection 9 isalso connected through a resistor 104 to ground. Ohmic connection 10 isconnected through a resistor 105 to an input terminal 106. Cooperatinginput terminal 107 is grounded. Connection 10 is also connected througha resistor 108 to ground. Ohmic connection 11 is connected through aresistor 109 and a biasing battery 110 to ground. Ohmic connection 8 isdirectly connected to ground.

Operation of Fig. 3

As in the case of the circuit Fig. 1, it is assumed that a binary 1input signal corresponds to an input potential of +5 volts and that abinary 0 input signal corresponds to an input potential of 0 volts. Itis essential that the transistor '1 be constructed so that one of thecollectors is favored over the other. Since the junction 4 is biasedforwardly by'ba tt ery 110, then if there is no input'signal at eitherof the sets of input terminals 102, 103 or 106, 107, the favoredcollector conducts, and sets up a potential gradient in the N region 2which effectively reduces the number of holes reaching the othercollector.

The table of Fig. 4 shows the state of the transistor 1 for variouscombinations of input signals, when the signal value of the inputpotential has a small value, for example, 5 volts. When there is noinput signal at either set of input terminals, as shown in line 1 of'Fig. 4, collector 5 is conducting and an output signal appears atterminals 19 and 20. Collector 6 is not conducting and no output signalappears at terminals .24 and 25. If, as in line 2 of Fig. 4, a positivesignal is now received at input terminal 102, it becomes effective toreverse bias the portion of the junction 4 opposite to collector 5.,thereby cutting off that collector, so that the holes emitted byjunction 4 HOW to collector 6, producing a signal at output terminals 24and 25.

The combination of input signals in line 3 of Fig. 4 restores the normalcondition of the output terminals. The collector 5 remains ON, and apositive input signal at terminal 106 tends to hold collector 6 OFF evenmore strongly.

When the input conditions are as indicated in the fourth line of Fig. 4,the two input signals balance one another and the conditions at theoutput terminals are again in their normal state as they would be ifthere were no input signals.

If an input signal of somewhat larger potential is used, for example 10volts, then the table of Fig. 5 may apply instead of the table of Fig.4. The two tables are identical except for their last line, when inputsignals are received at both sets of input terminals. If the inputsignal is sufficiently strong as compared to the biasing potential ofbattery 110, then that input signal may be elfective to turn thecollector 5 OFF, so that both collectors remain OFF at the same time.

Either the arrangement of Fig. 4 or the arrangement of Fig. 5 may beused as a non-commutative logical circuit. The arrangement of Fig. 4 isto be preferred, since it provides complementary outputs, either ofwhich distinguishes one particular combination of input signals from allother possible combinations of input signals.

While 1 have shown and described certain preferred embodiments of myinvention, other modifications thereof will readily occur to thoseskilled in the art and I therefore intend my invention to be limitedonly by the appended claims.

I claim:

1. A non-commutative logical circuit including a transistor comprising abody of semiconductive material including two thin regions ofsubstantially equal area and of opposite conductivity types, separatedby a boundary junction, one of said regions having a thicknesssubstantially no greater than the dilfusion length for the averagelifetime of minority carriers in the material thereof, the other of saidregions having a resistivity substantially lower than said one region,two collectors having high intrinsic current amplification in electricalcontact with said one region on the side thereof opposite said junction,said collectors being spaced by a distance substantially greater thansaid diffusion length, a pair of signal output means connectedrespectively to said two collectors, circuit means connected to saidother region for supplying current thereto, a pair of signal input.means connected to the opposite ends of said one region for controllingthe potential gradient thereacross, each signal input means beingshiftable independently of the other signal input means betweenseparated signal and nosignal potentials, said circuit means and thepair of signal input means cooperating to determine the polarity andmagnitude of the bias potentials across the portions of the junctionopposite the respective collectors, means connected to the collectorsfor supplying direct electrical energy thereto and eifective when bothsignal input means are at their no-signal potentials to hold one of thecollectors in a first stable state of conductivity, said pair of signalinput means being cooperating with said transistor body and said circuitmeans in only one other combination of input signals to shift said onecollector to a different stable state of conductivity.

2. A non-commutative logical circuit as defined in claim 1, in which thecurrent supply means includes means biasing the junction forwardly toemit minority carriers therefrom toward the collectors, and includingmeans in the transistor favoring the transmission of minority carriersfrom the junction to one of the collectors.

3. A non-commutative logical circuit as defined in claim 1, in which thesignals at the pair of signal output means are complementary.

References Cited in the file of this patent UNITED STATES PATENTS2,595,496 Webster May 6, 1952 2,641,717 Toth June 9, 1953 2,790,034McAtfee Apr. 23, 1957 2,795,744 Kircher June 11, 1957 2,801,348 PankoveJuly 30, 1957 2,854,588 Landauer Sept. 30, 1958 UNITED STATES PATENTOIFICE CERTIFICATE or CORRECTION Patent N00 2386 653 May 30 1961 I I 5Richard Fa Rutz It is hereby certified, that error appears in tie abovenumbered patent requiring correction and that the said Letters fatent,should read as corrected below Column l lines 18 and 19 for "358mb" read453 619 column 6 line 25, for 'effective" read cooper= atlng with saidtransistor body and said circuit means lines 28 and 29, for cooperatingwith said transistor body and said circuit means read effective e Signedand sealed this 24th day of O tober 1961o (SEAL);

Attest:

ERNEST W. SWIDER DAVID L. LADD Attesting Officer Commissioner of PatentsUSCOMM-DC-

